 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) FEATURES * * * * * * * * * * VCXO output for the 17MHz to 36MHz range Low phase noise (-130 dBc @ 10kHz offset at 35.328MHz). CMOS output with OE tri-state control. 17 to 36MHz fundamental crystal input. Integrated high linearity variable capacitors. 12mA drive capability at TTL output. +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. 2.5 to 3.3V operation. Available in 8-Pin SOIC, 6-pin SOT23 packages, or DIE. BLOCK DIAGRAM PIN CONFIGURATION XIN VDD* VIN GND 1 2 3 4 8 7 6 5 XOUT OE^ VDD* CLK ^: Denotes internal Pull-up *: Only one VDD pin needs to be connected PLL500-17 DESCRIPTION The PLL500-17 is a low cost, high performance and low phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 17 to 36MHz (fundamental resonant mode). OUT GND CLK 1 2 3 6 5 4 XIN VDD VIN PLL500-17 FREQUENCY RANGE MULTIPLIER No PLL FREQUENCY 17 - 36 MHz OUTPUT BUFFER CMOS 8-pin SOIC 6-pin SOT XIN XOUT XTAL OSC VARICAP OE VCON 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 1 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) DIE PAD LAYOUT 32 mil (812,986) DIE SPECIFICATIONS Name Value 8 1 XIN XOUT OE^ 7 39 mil 2 VDD VDD 6 Size Reverse side Pad dimensions Thickness 39 x 32 mil GND 80 micron x 80 micron 10 mil 3 VCON 4 GND CLK 5 DIE ID: PLL500-17: C500A0404-04A Y X (0,0) Note: ^ denotes internal pull up PIN ASSIGNMENT (8-pin SOIC package) AND PAD DESCRIPTION (8-pin SOIC package) Name XIN VDD VCON GND CLK VDD OE XOUT Pin# 1 2 3 4 5 6 7 8 Die Pad Position X (m) 94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906 Y (m) 768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881 Type I P I P O P I I Description Crystal input pin. VDD power supply pin. Only one VDD pin is necessary. Frequency control voltage input pin. Ground pin. Output clock pin. VDD power supply pin. Only one VDD pin is necessary. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Crystal output pin. Ref Clock input. * OE (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister. PIN ASSIGNMNET AND DESCRIPTION (6-pin SOIC package) Name XOUT GND CLK VCON VDD XIN Pin# 1 2 3 4 5 6 Type I P O I P I Description Crystal Output pin. Ref. Clock input. Ground pin. Output clock pin. Frequency control voltage input pin. VDD power supply pin. Crystal input pin. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 2 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Electrical Specifications PARAMETERS Input Crystal Frequency Output Clock Rise/Fall Time Output Clock Duty Cycle Short Circuit Current 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load Measured @ 1.4V 45 SYMBOL CONDITIONS MIN. 17 TYP. 1.15 3.7 50 50 MAX. 36 UNITS MHz ns 55 % mA 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity Power Supply Rejection VCON pin input impedance VCON modulation BW PWSRR SYMBOL TVCXOSTB CONDITIONS From power valid FXIN = 12 - 25MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V MIN. TYP. MAX. 10 UNITS ms ppm ppm ppm/V % ppm k kHz 300 150 100 5 Frequency change with VDD varied +/- 10% 0V VCON 3.3V, -3dB -1 2000 45 +1 Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. Jitter and Phase Noise Specifications 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 3 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) PARAMETERS RMS Period Jitter (1 sigma - 1000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier CONDITIONS With capacitive decoupling between VDD and GND. 36MHz @100Hz offset 36MHz @1kHz offset 36MHz @10kHz offset 36MHz @100kHz offset 36MHz @1MHz offset MIN. TYP. 2.5 -80 -110 -130 -138 -145 MAX. UNITS ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 5. DC Specifications PARAMETERS Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Low Voltage at CMOS level Output High Voltage at CMOS level Output drive current Short Circuit Current VCXO Control Voltage SYMBOL IDD VDD VOLC VOHC CONDITIONS FXIN = 36MHz Output load of 15pF MIN. TYP. 5 MAX. 6 3.63 0.4 UNITS mA V V V 2.25 IOL = +4mA IOH = -4mA For VOL<0.4V or VOH>2.4V VDD - 0.4 8 0 9.5 50 VCON VDD mA mA V 6. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating (VCON = 1.65V) Maximum Sustainable Drive Level Operating Drive Level C0 C0/C1 ESR SYMBOL FXIN CL (xtal) MIN. 17 TYP. 8.5 MAX. 36 200 UNITS MHz pF W W pF 50 5 250 30 RS Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 4 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) PACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol A A1 B C D E H L e Min. 1.47 0.10 0.33 0.19 4.80 3.80 5.80 0.38 Max. 1.73 0.25 0.51 0.25 4.95 4.00 6.20 1.27 1.27 BSC A 1 e B A C L D E H 6-pin SOT (Dimensions in mm) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 5 PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL500-17 X X R Part Number Package S=SOIC T= SOT D=Die NONE= TUBE R=TAPE and REEL Temperature C=Commercial I= Industrial Part / Order Number PLL500-17DC PLL500-17SC PLL500-17SC-R PLL500-17SCL PLL500-17SCL-R PLL500-17TC PLL500-17TC-R PLL500-17TCL PLL500-17TCL-R Marking P500-17DC P500-17 P500-17 P500-17L P500-17L P500-17 P500-17 P500-17L P500-17L Package Option Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 6-Pin SOT (Tube) 6-Pin SOT (Tape and Reel) 6-Pin SOT (Tube) 6-Pin SOT (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/21/05 Page 6 |
Price & Availability of PLL500-17
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |